1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a duty cycle correction circuit.
2. Related Art
A semiconductor memory apparatus may operate in synchronization with a clock signal. Here, the clock signal would be understood as an ideal clock signal if a high level duration and a low level duration have the same length.
In order to generate a clock signal with a high level duration and a low level duration having the same length, a semiconductor memory apparatus may have a duty cycle correction circuit.